1/9 september 2001 n 5v tolerant inputs n high speed : t pd = 6.7ns (max.) at v cc = 3v n power down protection on inputs and outputs n symmetrical output impedance: |i oh | = i ol = 24ma (min) at v cc = 3v n pci bus levels guaranteed at 24 ma n balanced propagation delays: t plh @ t phl n operating voltage range: v cc (opr) = 2.0v to 3.6v (1.5v data retention) n pin and function compatible with 74 series 138 n latch-up performance exceeds 500ma (jesd 17) n esd performance: hbm > 2000v (mil std 883 method 3015); mm > 200v description the 74lcx138 is a low voltage cmos 3 to 8 line decoder (inverting) fabricated with sub-micron silicon gate and double-layer metal wiring c 2 mos technology. it is ideal for low power and high speed 3.3v applications; it can be interfaced to 5v signal environment for inputs. if the device is enabled, 3 binary select inputs (a, b and c) determine which one of the outputs will go low. if enable input g1 is held low or either g2a or g2b is held high, the decoding function is ihnibited and all the 8 outputs go to high. three enable inputs are provided to ease cascade connection and application of address decoders for memory systems. it has same speed performance at 3.3v than 5v ac/act family, combined with a lower power consumption. all inputs and outputs are equipped with protection circuits against static discharge, giving them 2kv esd immunity and transient excess voltage. 74lcx138 low voltage cmos 3 to 8 line decoder (inv.) with 5v tolerant inputs pin connection and iec logic symbols order codes package tube t & r sop 74LCX138M 74LCX138Mtr tssop 74lcx138ttr tssop sop
74lcx138 2/9 input and output equivalent circuit pin description truth table x : dont care pin no symbol name and function 1, 2, 3 a, b, c address inputs 4, 5 g2a , g2b enable inputs 6 g1 enable input 15, 14, 13, 12, 11, 10, 9, 7 y0 to y7 outputs 8 gnd ground (0v) 16 v cc positive supply voltage inputs outputs enable select g2b g2a g1cbay0 y1 y2 y3 y4 y5 y6 y7 xx l xxxhhhhhhhh xhxxxx hhhhhhhh hxxxxx hhhhhhhh llhllll hhhhhhh llhllhhlhhhhhh llhlhlhhlhhhhh l lhlhhhhhlhhhh l lhhl lhhhhl hhh l lhhlhhhhhh lhh l lhhhlhhhhhhlh l lhhhhhhhhhhhl
74lcx138 3/9 logic diagram this logic diagram has not be used to estimate propagation delays absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditi ons is not implied 1) i o absolute maximum rating must be observed 2) v o < gnd recommended operating conditions 1) truth table guaranteed: 1.5v to 3.6v 2) v in from 0.8v to 2v at v cc = 3.0v symbol parameter value unit v cc supply voltage -0.5 to +7.0 v v i dc input voltage -0.5 to +7.0 v v o dc output voltage (v cc = 0v) -0.5 to +7.0 v v o dc output voltage (high or low state) (note 1) -0.5 to v cc + 0.5 v i ik dc input diode current - 50 ma i ok dc output diode current (note 2) - 50 ma i o dc output current 50 ma i cc dc supply current per supply pin 100 ma i gnd dc ground current per supply pin 100 ma t stg storage temperature -65 to +150 c t l lead temperature (10 sec) 300 c symbol parameter value unit v cc supply voltage (note 1) 2.0 to 3.6 v v i input voltage 0 to 5.5 v v o output voltage (v cc = 0v) 0 to 5.5 v v o output voltage (high or low state) 0 to v cc v i oh , i ol high or low level output current (v cc = 3.0 to 3.6v) 24 ma i oh , i ol high or low level output current (v cc = 2.7v) 12 ma t op operating temperature -55 to 125 c dt/dv input rise and fall time (note 2) 0 to 10 ns/v
74lcx138 4/9 dc specifications dynamic switching characteristics 1) number of outputs defined as "n". measured with "n-1" outputs switching from high to low or low to high. the remaining outpu t is measured in the low state. symbol parameter test condition value unit v cc (v) -40 to 85 c -55 to 125 c min. max. min. max. v ih high level input voltage 2.7 to 3.6 2.0 2.0 v v il low level input voltage 0.8 0.8 v v oh high level output voltage 2.7 to 3.6 i o =-100 m av cc -0.2 v cc -0.2 v 2.7 i o =-12 ma 2.2 2.2 3.0 i o =-18 ma 2.4 2.4 i o =-24 ma 2.2 2.2 v ol low level output voltage 2.7 to 3.6 i o =100 m a 0.2 0.2 v 2.7 i o =12 ma 0.4 0.4 3.0 i o =16 ma 0.4 0.4 i o =24 ma 0.55 0.55 i i input leakage current 2.7 to 3.6 v i = 0 to 5.5v 5 5 m a i off power off leakage current 0 v i or v o = 5.5v 10 10 m a i cc quiescent supply current 2.7 to 3.6 v i = v cc or gnd 10 10 m a v i or v o = 3.6 to 5.5v 10 10 d i cc i cc incr. per input 2.7 to 3.6 v ih = v cc - 0.6v 500 500 m a symbol parameter test condition value unit v cc (v) t a = 25 c min. typ. max. v olp dynamic low level quiet output (note 1) 3.3 c l = 50pf v il = 0v, v ih = 3.3v 0.8 v v olv -0.8
74lcx138 5/9 ac electrical characteristics 1) skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch- ing in the same direction, either high or low (t oslh = | t plhm - t plhn |, t oshl = | t phlm - t phln |) 2) parameter guaranteed by design capacitive characteristics 1) c pd is defined as the value of the ics internal equivalent capacitance which is calculated from the operating current consumption without load. (refer to test circuit). average operating current can be obtained by the following equation. i cc(opr) = c pd x v cc x f in + i cc test circuit c l = 50pf or equivalent (includes jig and probe capacitance) r l = 500 w or equivalent r t = z out of pulse generator (typically 50 w ) symbol parameter test condition value unit v cc (v) c l (pf) r l ( w ) t s = t r (ns) -40 to 85 c -55 to 125 c min. max. min. max. t plh t phl propagation delay time a, b, c to y 2.7 50 500 2.5 7.9 7.9 ns 3.0 to 3.6 1.5 6.7 1.5 6.7 t plh t phl propagation delay time g1 to y 2.7 50 500 2.5 6.4 6.4 ns 3.0 to 3.6 1.5 5.8 1.5 5.8 t plh t phl propagation delay time g2 to y 2.7 50 500 2.5 7.4 7.4 ns 3.0 to 3.6 1.5 6.5 1.5 6.5 t oslh t oshl output to output skew time (note1, 2) 3.0 to 3.6 50 500 2.5 1.0 1.0 ns symbol parameter test condition value unit v cc (v) t a = 25 c min. typ. max. c in input capacitance 3.3 v in = 0 to v cc 6pf c pd power dissipation capacitance (note 1) 3.3 f in = 10mhz v in = 0 or v cc 42 pf
74lcx138 6/9 waveform 1 : propagation delays for inverting outputs (f=1mhz; 50% duty cycle) waveform 2: propagation delays for non-inverting outputs (f=1mhz; 50% duty cycle)
74lcx138 7/9 dim. mm. inch min. typ max. min. typ. max. a 1.75 0.068 a1 0.1 0.2 0.003 0.007 a2 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 c 0.5 0.019 c1 45 (typ.) d 9.8 10 0.385 0.393 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 f 3.8 4.0 0.149 0.157 g 4.6 5.3 0.181 0.208 l 0.5 1.27 0.019 0.050 m 0.62 0.024 s8 (max.) so-16 mechanical data po13h
74lcx138 8/9 dim. mm. inch min. typ max. min. typ. max. a 1.2 0.047 a1 0.05 0.15 0.002 0.004 0.006 a2 0.8 1 1.05 0.031 0.039 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 d 4.9 5 5.1 0.193 0.197 0.201 e 6.2 6.4 6.6 0.244 0.252 0.260 e1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 bsc 0.0256 bsc k0 80 8 l 0.45 0.60 0.75 0.018 0.024 0.030 tssop16 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 0080338d
74lcx138 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2000 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco singapore - spain - sweden - switzerland - united kingdom ? http://www.st.com 9/9
|
